• SHAIK JAGADEESH BABU
• V. KIRANMAI
• B. REVATHI
• B. HARSHITHA
• B. V BHAGYA LAKSHMI

Three operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and pseudorandom bit generator (PRBG) algorithms. Carry save adder (CS3A) is the widely used technique to perform the three-operand addition. However, the ripple-carry stage in the CS3A leads to a high propagation delay. Moreover, a parallel prefix two operand adder such as Han-Carlson (HCS) can also be used for three-operand addition that significantly reduces the critical path delay at the cost of additional hardware Hence, a new high-speed and area-efficient adder architecture is proposed using pre-compute bitwise addition that consumes substantially less area, low power and drastically reduces the adder delay. Moreover, it has a smaller delay than the HC3A adder. Also, the proposed adder achieves the lowest ADP and PDP than the existing three-operand adder techniques.

Three-operand adder, carry save adder (CSA), Han-Carlson adder (HCA), modular arithmetic

"HIGH SPEED AREA-EFFICIENT VLSI ARCHITECTURE OF THREE OPERAND BINARY ADDER ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 5, page no.a446-a451, May-2025, Available :http://www.jetir.org/papers/JETIR2505046.pdf

"HIGH SPEED AREA-EFFICIENT VLSI ARCHITECTURE OF THREE OPERAND BINARY ADDER ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 5, page no. ppa446-a451, May-2025, Available at : http://www.jetir.org/papers/JETIR2505046.pdf