• KARANAM SOWJANYA
• Y. RAVI KIRAN VARMA

Multipliers are vital in high-speed computing systems, especially in digital signal processing, image processing, and embedded applications. However, traditional multiplier designs often suffer from high power consumption and large area, limiting their effectiveness in modern low-power VLSI environments. This paper presents a novel low-power Radix-8 Booth multiplier architecture that significantly reduces the number of partial products and incorporates efficient compressor adders, glitch correction, and clock gating mechanisms. The proposed design is implemented using VHDL and synthesized on FPGA. The simulation results confirm reduced power consumption, minimized delay, and optimized area, making it suitable for energy-efficient and high-speed arithmetic applications.

"DESIGN AND IMPLEMENTATION OF A LOW POWER RADIX-8 BOOTH MULTIPLIER FOR HIGH-SPEED ARITHMETIC OPERATIONS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 5, page no.d845-d848, May-2025, Available :http://www.jetir.org/papers/JETIR2505443.pdf

"DESIGN AND IMPLEMENTATION OF A LOW POWER RADIX-8 BOOTH MULTIPLIER FOR HIGH-SPEED ARITHMETIC OPERATIONS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 5, page no. ppd845-d848, May-2025, Available at : http://www.jetir.org/papers/JETIR2505443.pdf