• Chellu Varshitha
• DR G Elaiyaraja

In modern digital systems, efficient decision-making mechanisms are essential for improving performance and minimizing energy consumption. This paper proposes a novel majority voting architecture using approximate computing techniques. By integrating approximate adder trees, early stopping conditions, and logarithmic pipelining, the design significantly reduces hardware complexity, area, and dynamic power consumption. Implemented on FPGA using Xilinx Vivado, the proposed architecture achieves over 60% area reduction and nearly 50% dynamic power savings compared to traditional methods, while maintaining decision accuracy. This makes it suitable for energy-constrained applications such as IoT and embedded AI.

Majority Voting, Approximate Computing, FPGA, Low Power Design, Digital Hardware, Ensemble Learning.

"Majority Voting in Digital Hardware ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 5, page no.g796-g800, May-2025, Available :http://www.jetir.org/papers/JETIR2505781.pdf

"Majority Voting in Digital Hardware ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 5, page no. ppg796-g800, May-2025, Available at : http://www.jetir.org/papers/JETIR2505781.pdf