UGC Approved Journal no 63975(19)
New UGC Peer-Reviewed Rules

ISSN: 2349-5162 | ESTD Year : 2014
Volume 12 | Issue 10 | October 2025

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Published in:

Volume 12 Issue 8
August-2025
eISSN: 2349-5162

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Published Paper ID:
JETIR2508181


Registration ID:
567113

Page Number

b618-b631

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Title

FPGA-Based Morse Code Encoder with Slide Switch Input and Dual LED-Segment Display

Abstract

This paper presents an innovative, real-time Morse code encoder implemented on the Digilent Basys 3 Field Programmable Gate Array (FPGA) using Verilog Hardware De- scription Language (HDL). The system leverages six slide switches to input a 6-bit bi- nary code, encoding 39 characters (A–Z, 0–9, period, comma, question mark), mapped to standardized Morse code patterns displayed on six Light Emitting Diodes (LEDs). A novel combinational lookup table decodes inputs into 6-bit Morse patterns and 7-bit timing counts, serialized via a Finite State Machine (FSM) adhering to precise timing standards: 100 ms dots, 300 ms dashes, and 100 ms inter-element gaps. A clock divider transforms the 100 MHz system clock to 10 Hz, ensuring deterministic timing. The sys- tem features a seven-segment display for character visualization, enhancing user inter- action, and a fault-tolerant mechanism that blanks LEDs and displays ’Err’ for invalid inputs (sw[5:0] ¿ 39 or 0). Synthesized on the Xilinx Artix-7 XC7A35T, the design achieves ultra-low resource utilization (0.74% LUTs, 0.44% flip-flops) and meets 100 MHz timing constraints with 3.5 ns slack. Validated through Vivado simulation and hardware testing, the encoder delivers glitch-free operation using stable slide switch inputs, eliminating debouncing needs. Its modular architecture supports extensions like wireless UART transmission and audio output via Pulse Width Modulation (PWM), offering scalability for educational platforms and low-bandwidth communication sys- tems. This work advances FPGA-based signal processing by integrating high-speed digital logic, real-time feedback, and error handling, making it a robust solution for teaching digital design and developing reliable communication interfaces in resource- constrained environments.

Key Words

FPGA, Morse code encoder, Verilog HDL, slide switches, LED output, seven-segment display, Finite State Machine, real-time processing, timing control

Cite This Article

"FPGA-Based Morse Code Encoder with Slide Switch Input and Dual LED-Segment Display", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 8, page no.b618-b631, August-2025, Available :http://www.jetir.org/papers/JETIR2508181.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"FPGA-Based Morse Code Encoder with Slide Switch Input and Dual LED-Segment Display", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 8, page no. ppb618-b631, August-2025, Available at : http://www.jetir.org/papers/JETIR2508181.pdf

Publication Details

Published Paper ID: JETIR2508181
Registration ID: 567113
Published In: Volume 12 | Issue 8 | Year August-2025
DOI (Digital Object Identifier):
Page No: b618-b631
Country: Mangalagiri, Andhra Pradesh, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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