• J. Aparna
• C. R. K. Gayatri

The design of a high-performance, five-stage, 32-bit microprocessor that operates without interlocked pipeline stages (MIPS) and follows the Reduced Instruction Set Computing (RISC) architecture has presented. The primary objective of a RISC-based microprocessor is to efficiently execute a limited set of instructions, thereby enhancing processing speed. The CPU pipeline is structured into five key stages: Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory Access (MEM), and Write Back (WB). Various functional modules, including the Arithmetic Logic Unit (ALU), Control Unit, Program Counter, Multiplexer (MUX), Instruction Memory, Register File, Sign Extension, and Data Memory, are incorporated to facilitate execution and address calculation. The design is implemented using a Hardware Description Language (HDL) and is developed using Xilinx for constructing an RTL (Register Transfer Level) logic design.

RISC, MIPS, ISA, CISC, Simulation

"Design and Implementation of 32-Bit RISC Processor Using VHDL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 9, page no.d228-d232, September-2025, Available :http://www.jetir.org/papers/JETIR2509334.pdf

"Design and Implementation of 32-Bit RISC Processor Using VHDL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 9, page no. ppd228-d232, September-2025, Available at : http://www.jetir.org/papers/JETIR2509334.pdf