• Ms. Gandi Prathyusha
• Velaga Suryakala

This research proposes a novel hierarchical architecture for a 16-bit Arithmetic Logic Unit (ALU) aimed at achieving significant energy efficiency through a combination of adaptive clock gating, Dynamic Voltage and Frequency Scaling (DVFS), and multi-level power domain partitioning. The proposed ALU is divided into two primary functional units — Arithmetic Unit and Logical Unit — each further subdivided into smaller sub-blocks to enable fine-grained power management. A demultiplexer-based selector dynamically applies clock signals only to active functional units, while adaptive clock gating ensures that inactive sub-blocks within each unit are powered down during idle periods. To enhance scalability and energy efficiency, the architecture incorporates hierarchical clock gating, where clocks are gated at multiple levels (functional unit and sub-block) based on real-time workload demands. The design also integrates thermal-aware DVFS, which dynamically adjusts the operating voltage and frequency of individual functional units according to workload intensity and thermal constraints, ensuring optimal performance while maintaining safe operating temperatures. Additionally, the architecture introduces partitioned power domains, allowing independent voltage and frequency scaling for each functional unit, thereby minimizing unnecessary power consumption in unused blocks. Extensions such as predictive workload monitoring and fine-grained pipeline partitioning are incorporated to further optimize energy efficiency and performance. The proposed architecture is designed for scalability, making it suitable for integration into larger systems such as Networks-on-Chip (NoCs) or Systems-on-Chip (SoCs). By combining these advanced techniques, the model achieves a highly efficient and modular design capable of addressing the power and thermal challenges of modern VLSI systems. This work highlights the potential of the proposed architecture for applications in battery-powered devices, high-performance computing, and thermal management.

Adaptive Clock Gating, Dynamic Voltage and Frequency Scaling (DVFS), Hierarchical Power Management, 16-bit ALU, Thermal-Aware Design, Multi-Level Clock Gating, Partitioned Power Domains, Predictive Workload Monitoring, Fine-Grained Pipeline Partitioning, Energy Efficiency, Low-Power VLSI Design.

"Energy-Efficient 16-bit ALU Design Using Clock Gating and Dynamic Voltage-Frequency Scaling (DVFS)", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 9, page no.f306-f315, September-2025, Available :http://www.jetir.org/papers/JETIR2509540.pdf

"Energy-Efficient 16-bit ALU Design Using Clock Gating and Dynamic Voltage-Frequency Scaling (DVFS)", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 9, page no. ppf306-f315, September-2025, Available at : http://www.jetir.org/papers/JETIR2509540.pdf