• Mrs. GUDLA VANAJA
• Dr. R. Suneetha

In modern digital systems, efficient multiplication plays a crucial role in performance optimization. This paper presents a Modified Vedic Multiplier design, which incorporates the Carry Look ahead Adder to improve the speed and power efficiency compared to the traditional Vedic multiplier that uses a Ripple Carry Adder (RCA). The proposed Modified Vedic Multiplier leverages the parallel processing capabilities of Vedic mathematics for fast multiplication and enhances the carry propagation delay using the Carry Look ahead Adder, known for its low-latency and fast carry generation. The Carry Look ahead Adder ’s parallel carry generation significantly reduces the critical path delay, improving the overall speed of the multiplier. In contrast, the conventional Vedic multiplier with an RCA suffers from slower carry propagation, resulting in higher delay. Simulation results show that the Modified Vedic Multiplier with the Carry Look ahead Adder performs the Vedic multiplier using the Ripple Carry Adder in terms of speed, area, and power consumption. The proposed design provides a more efficient solution for high-speed, low-power digital systems, making it suitable for applications in signal processing, cryptography, and embedded systems.

Vedic algorithm , carry look ahead adder, VLSI architecture and Verilog HDL.

"AREA AND POWER OPTIMIZED VLSI ARCHITECTURE OF VEDIC MULTIPLIER USING CARRY LOOK A HEAD ADDER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 10, page no.c469-c475, October-2025, Available :http://www.jetir.org/papers/JETIR2510262.pdf

"AREA AND POWER OPTIMIZED VLSI ARCHITECTURE OF VEDIC MULTIPLIER USING CARRY LOOK A HEAD ADDER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 10, page no. ppc469-c475, October-2025, Available at : http://www.jetir.org/papers/JETIR2510262.pdf