• Kadali Hari Krishna
• Ch.Venkata Rao

Arithmetic units, particularly multipliers, significantly influence the performance, power efficiency, and silicon area utilization of modern Very Large-Scale Integration (VLSI) systems. Conventional multiplier designs based on CMOS logic suffer from high power consumption and large area requirements, which limit their suitability for low-power and area-constrained applications such as portable electronics, embedded systems, and Internet of Things (IoT) devices. This paper presents a novel 8-bit signed multiplier architecture employing Pass Transistor Logic (PTL) to enhance area and power efficiency. By utilizing PTL, the proposed design reduces transistor count and dynamic power dissipation through direct signal propagation, eliminating the need for complementary pull-up and pull-down networks typical of CMOS logic. The optimized architecture maintains signal integrity while minimizing propagation delay and silicon footprint. Post-layout simulations under various operating conditions demonstrate notable reductions in power consumption and area compared to conventional CMOS-based multipliers, without compromising speed or accuracy. The proposed PTL-based multiplier achieves a lower power-delay product (PDP), confirming its effectiveness for energy-efficient and compact VLSI applications.

Pass Transistor Logic (PTL), 8-bit signed multiplier, low-power design

"AREA AND POWER OPTIMIZATION OF AN 8-BIT SIGNED MULTIPLIER USING PASS TRANSISTOR LOGIC(PTL)", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 10, page no.c476-c486, October-2025, Available :http://www.jetir.org/papers/JETIR2510263.pdf

"AREA AND POWER OPTIMIZATION OF AN 8-BIT SIGNED MULTIPLIER USING PASS TRANSISTOR LOGIC(PTL)", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 10, page no. ppc476-c486, October-2025, Available at : http://www.jetir.org/papers/JETIR2510263.pdf