• PALLA VENKATALAKSHMI
• S.SHARMILA BANU

An integral part of processors, the Arithmetic Logic Unit (ALU) performs arithmetic and logical operations that are necessary for the design of digital systems. In this study, a 64-bitALU with 16 operations is designed in Verilog HDL. Each one-bit ALU unit is constructed using logical gates like AND and OR. This design achieves lower power consumption and higher speed in comparison to traditional ALUs.To further improve energy economy in low-power VLSI systems, reversible logic which is known for its power-efficient properties is incorporated into the design. Performance measurements demonstrate the advantages of the suggested 64-bit reversible ALU over conventional ALU architectures when it is synthesized and simulated using Xilinx Vivado.

Keywords: Reversible gate, Verilog HDL, Feynman gate, Peres gate, Toffoli gate, Fredkin gate, Arithmetic Logic Unit.

"64-BIT ALU BASED ON FPGAUSING REVERSIBLE LOGIC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 11, page no.c673-c683, November-2025, Available :http://www.jetir.org/papers/JETIR2511283.pdf

"64-BIT ALU BASED ON FPGAUSING REVERSIBLE LOGIC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 11, page no. ppc673-c683, November-2025, Available at : http://www.jetir.org/papers/JETIR2511283.pdf