• Abhishek Kumar
• Manisha Kumari Singh

This paper presents a comprehensive survey of techniques for modeling and improving Memory Level Parallelism (MLP), an increasingly important factor in enhancing modern processor performance. While traditional approaches have focused mainly on instruction-level optimizations, this review highlights how the ability to handle multiple memory accesses simultaneously plays a key role in overcoming memory bottlenecks. The survey summarizes major developments in cache behavior modeling, processor performance analysis, and a range of analytical, experimental, and mechanistic MLP models. It also reviews architectural methods that help extract higher MLP, including advanced out-of-order execution strategies, slice-based designs, and prefetching mechanisms. The paper concludes by identifying gaps in existing research particularly in multicore and GPU environments and outlines promising future directions for building more accurate, scalable, and energy-aware MLP modeling frameworks.

Memory Level Parallelism, Prefetching, Single Core Architecture, Multicore Architecture, Miss Rate

"A Comprehensive Survey of Techniques of Modelling and Extracting Memory Level Parallelism", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 11, page no.f341-f348, November-2025, Available :http://www.jetir.org/papers/JETIR2511561.pdf

"A Comprehensive Survey of Techniques of Modelling and Extracting Memory Level Parallelism", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 11, page no. ppf341-f348, November-2025, Available at : http://www.jetir.org/papers/JETIR2511561.pdf