• P.RAJENDRA

This project explores the design and ASIC implementation of an image classifier CNN accelerator using the ASAP 7nm process. It describes an end-to-end hardware flow, focusing on detailed architecture optimization with convolution, pooling, activation, and FC units; pipelining; and clock gating. Synthesis results show that this design achieves a high frequency, low latency, and energy efficiency superior to existing solutions such as GPUs and FPGAs. The proposed chip is thus well-suited for real-time inference on power-constrained embedded systems.

ASIC, CNN, Cadence, Hardware Accelerator, ASAP 7nm.

"DESIGN AND IMPLEMENTATION OF CNN FOR IMAGE CLASSIFICATION ON ASAP 7NM TECHNOLOGY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 12, page no.b621-b625, December-2025, Available :http://www.jetir.org/papers/JETIR2512178.pdf

"DESIGN AND IMPLEMENTATION OF CNN FOR IMAGE CLASSIFICATION ON ASAP 7NM TECHNOLOGY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 12, page no. ppb621-b625, December-2025, Available at : http://www.jetir.org/papers/JETIR2512178.pdf