UGC Approved Journal no 63975(19)
New UGC Peer-Reviewed Rules

ISSN: 2349-5162 | ESTD Year : 2014
Volume 12 | Issue 12 | December 2025

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Published in:

Volume 12 Issue 12
December-2025
eISSN: 2349-5162

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Published Paper ID:
JETIR2512295


Registration ID:
573125

Page Number

c813-c820

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Title

Implementation of 64 Bit Vedic Multiplier Using Brent Kung Adder and Reversible Logic Gates

Abstract

In daily life, there is a rise in technology improvement; each application we utilize operates with great speed and mobility. The performance of these devices is contingent upon the efficacy of the embedded processor. Multipliers are regarded as one of the essential components of every CPU. The efficiency of the devices is significantly determined by the computing speed, methodology, and power efficiency of the used multiplier. Given that Very Large Scale Integration (VLSI) is capable of executing many functions, the performance of the system mostly depends on the multiplier circuit; therefore, the primary aim of designing a multiplier is to minimize power consumption and delay. This thesis primarily focuses on the development of multipliers that are minimal in power consumption, area, and delay. Reversible logic is recognized as a distinctive and advantageous method for power-efficient computation. The primary issue in reversible circuit design is to reduce trash outputs and constant inputs. Quantum computers provide a viable alternative to classical systems. The thesis has thus far outlined the theoretical framework for implementing and assessing the reversible multiplier. The aim of this study is to develop an improved Vedic multiplier utilizing innovative and efficient reversible logic gates and Brent-Kung adders.

Key Words

Brent Kung Adder, Carry Select Adder, Reversible Logics, Vedic Multiplier, VLSI.

Cite This Article

"Implementation of 64 Bit Vedic Multiplier Using Brent Kung Adder and Reversible Logic Gates", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 12, page no.c813-c820, December-2025, Available :http://www.jetir.org/papers/JETIR2512295.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Implementation of 64 Bit Vedic Multiplier Using Brent Kung Adder and Reversible Logic Gates", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 12, page no. ppc813-c820, December-2025, Available at : http://www.jetir.org/papers/JETIR2512295.pdf

Publication Details

Published Paper ID: JETIR2512295
Registration ID: 573125
Published In: Volume 12 | Issue 12 | Year December-2025
DOI (Digital Object Identifier):
Page No: c813-c820
Country: Indore, MP, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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