• Niketa Sahu
• Dr. Megha Soni

In Multiplication is a vital operation in digital signal processing units, fundamental for high-speed communication networks and multimedia applications. The design of high-speed integrated circuits with reduced power consumption is a primary problem for VLSI circuit designers. Full adders are predominantly utilized for various arithmetic operations in digital circuits and constitute the principal component that expends a considerable quantity of power. Determining the ideal multiplier architecture is a crucial factor in the construction of a Digital Signal Processor. Multipliers are the principal factors in power consumption inside digital signal processing. Reducing the multiplier's power usage may diminish the digital signal processor's power consumption throughout a broad spectrum. This paper seeks to examine and develop high-performance, rapid, and energy-efficient multipliers. An examination was performed on the area and power consumption of several adders, which serve as the essential components of a multiplier. According to the literature, Dadda multipliers have strong performance when combined with Brent Kung adders, indicating a notable advancement for high-speed parallel processing applications. The use of Kung-Brent adders in Dadda multipliers improves the speed of addition operations, optimizing the critical route for enhanced performance.

Dadda Multiplier, Brent Kung Adder, Carry Select Adders, VLSI.

"Improved 16 Bit Dadda Multiplier using Brent Kung Adder for Fast Processing ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 12, page no.d83-d91, December-2025, Available :http://www.jetir.org/papers/JETIR2512312.pdf

"Improved 16 Bit Dadda Multiplier using Brent Kung Adder for Fast Processing ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 12, page no. ppd83-d91, December-2025, Available at : http://www.jetir.org/papers/JETIR2512312.pdf