• Reddi sekhar
• T.Rajasree
• V.Hemalatha
• R.Ashok kumar
• G.Mahesh Naidu

Present we are designing Double Error Correction (DEC) codes for 32-bit data words that support fast decoding as they can be useful to protect memories. We are used previously Orthogonal Latin Square codes have been recently presented that achieve fast decoding but require a large number of parity check bits. In this present work, a DEC code derived from Difference Set codes is presented. The proposed code is able to reduce the number of parity check bits needed at the cost of a slightly more complex decoding. Therefore, it provides memory designers with an additional option that can be useful between memory size and speed.

Error correction codes, memories, Difference Set codes, Orthogonal Latin Square codes

"A DOUBLE ERROR CORRECTION CODES WITH LESS NUMBER OF PARITY BITS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 3, page no.170-174, March-2019, Available :http://www.jetir.org/papers/JETIRAK06031.pdf

"A DOUBLE ERROR CORRECTION CODES WITH LESS NUMBER OF PARITY BITS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 3, page no. pp170-174, March-2019, Available at : http://www.jetir.org/papers/JETIRAK06031.pdf