• K.Lakshmi Bhanu Prakash Reddy
• K.Pravallika
• A.Sri Harika
• G.Pavana Manjari
• M.thulasi Priya

In this technical world, sequential circuits are playing their major role in the designing of digital systems. A counter is a sequential circuit having different applications in the field of embedded system, pattern generations, signal synthesis, Digital to Analog conversion etc. Sequential circuit design with less power and high speed at smaller chip size has become the main concern for researcher and day by day development in VLSI technologies also help the flow for achieving the required goals. In this paper, an optimized designing mechanism has been positioned to design a high speed, cost effective and low power 4-bit ring counter which can also be extended to higher sequence ring counter designs. In this design, performance of the proposed ring counter is implemented by using a negative edge triggered master slave D flip flop which consists of 14 MOS transistors in its design as compare to conventional counter. The proposed paper has practised the design goals by decreasing the 68.19% transistor count, 56.63% power consumption and occupies the 62.816% less area.

Ring Counter; Master slave D flip flop; negative Edge trigged; ; CMOS gates Transistor count; VLSI power dissipation.

"HYBRID OPTIMIZED DESIGN AND SIMULATION OF NEGATIVE EDGE TRIGGER RING COUNTER USING 45nm TECHNOLOGY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 3, page no.196-203, March-2019, Available :http://www.jetir.org/papers/JETIRAK06036.pdf

"HYBRID OPTIMIZED DESIGN AND SIMULATION OF NEGATIVE EDGE TRIGGER RING COUNTER USING 45nm TECHNOLOGY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 3, page no. pp196-203, March-2019, Available at : http://www.jetir.org/papers/JETIRAK06036.pdf