• S.Nagaraju
• B.Guru Raja
• C.Mahendra Babu
• R.Aravinda Reddy
• G.Karthik

Modern Network Intrusion Detection System needs a high throughput and low power pattern matching system to meet present high speed wireless communication systems. In this paper Field Programmable Gate Array(FPGA) hardware based NIDS system is introduced to reduce the delay and power to increase the performance of the system. Here a bit based parallel pattern matching algorithm is used to reduce the computational complexity through early detection which leads to less SRAM memory requirement and low power. The bit wise matching process takes place in 8 single bit FSM’s rather than string based approach. Here an All Digital Phase Locked Loop (ADPLL) is used to generate multirate clock without using analog circuitry for matching with input payload with an existing virus signatures having in SRAM database. The simulation results are verified using Modelsim 6.4a.

NIDS, ADPLL, Pattern Matching, FPGA, SRAM cell, FSM(Finite State Machine

"LOW POWER MULTIRATE NETWORK INTRUSION DETECTION SYSTEM USING SRAM CONTROLLER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 3, page no.229-233, March-2019, Available :http://www.jetir.org/papers/JETIRAK06042.pdf

"LOW POWER MULTIRATE NETWORK INTRUSION DETECTION SYSTEM USING SRAM CONTROLLER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 3, page no. pp229-233, March-2019, Available at : http://www.jetir.org/papers/JETIRAK06042.pdf