• Mr. M.Mahesh Kumar
• Ms. T Aneela
• Ms. SK Sana
• Ms. SK Shahina
• Ms. C vijitha

Emerging Non Volatile Memories (NVMs), such as PRAM, MRAM and RRAM, as well as a wide array of field-programmable gate for greater security and immediate energy arrays (FPGAs) have been investigated in place of SRAM configuration bits. However, NVMs and variations inherent in the procedure of modern logic, FPGAs bring to a matter of credibility. This is neither a matter of credibility, tolerating diversity to overcome a low-power Non Volatile Look up Table (NVLUT) circuit contact. Because of the large ROFF / RON, 1T1R RRAM cell pattern bit and reference resistor provides a sufficient margin of sense. The clamp voltage without impairing the reliability of a single-stage sense amplifier is employed to reduce power and area. Matched the forecast path for reliable sensing the parasitic RC proposed to reduce the imbalance. A reduction of 22% to 38% diminution in the delay in the evaluation of the power, and reliability of the 2.5 × typical RON or ROFF tolerance.

low power, high speed, RRAM, FPGA- (Field Programmable Gate Array), non- volatile SRAM (nvSRAM).

"LOW POWER CONSUMPTION USING NON VOLATILE RRAM LOOKUP TABLES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.48-53, April-2019, Available :http://www.jetir.org/papers/JETIRBC06008.pdf

"LOW POWER CONSUMPTION USING NON VOLATILE RRAM LOOKUP TABLES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp48-53, April-2019, Available at : http://www.jetir.org/papers/JETIRBC06008.pdf