• M.Mahesh Kumar
• C.Srinath
• K.Bobby
• K.Yaswanth
• G.Manideep

In this paper, a new very-large-scale integrated (VLSI) integer transform architecture is proposed for the High Efficiency Video Coding (HEVC) encoder. The architecture is designed based on the signed bit-plane transform (SBT) matrices, which are derived from the bit-plane decompositions of the integer transform matrices in HEVC. Mathematically, an integer transform matrix can be equally expressed by the binary weighted sum of several SBT matrices that are only composed of binary 0 or 1. The SBT matrices are very simple and have lower bit width than the original integer transform in the form. The SBT matrices are also sparse and there are many zero elements. The sparse characteristic of SBT matrices is very helpful for saving the addition operators of SBT. In the proposed architecture, instead of the original integer transform in high bit width, the video data can be respectively transformed with the SBT matrices in lower bit width. As a result, the delay of the transform unit circuit can be significantly reduced with the proposed SBT.

HEVC, SBT

" A BIT-PLANE DECOMPOSITION MATRIX-BASED VLSI INTEGER TRANSFORM ARCHITECTURE FOR HEVC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.124-130, April-2019, Available :http://www.jetir.org/papers/JETIRBC06019.pdf

" A BIT-PLANE DECOMPOSITION MATRIX-BASED VLSI INTEGER TRANSFORM ARCHITECTURE FOR HEVC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp124-130, April-2019, Available at : http://www.jetir.org/papers/JETIRBC06019.pdf