• Ramanatham UmaMaheswari
• Ganekanti Naresh
• Neelima K

The abstract should summarize the contents of the paper and should contain A 4bit multiplier is implemented by using Dadda multiplier to achieve the performance characters the limitations of an IC technology. In this paper, discussed about Wallace tree multiplier and Dadda algorithm. The parameters like power dissipation and delay are better in Dadda algorithm when compare to Wallace tree multiplier. An optimized transistor level design for internal logic i.e., for AND Gate, XOR Gate and Full Adders are developed. The designs are modelled in SPICE and their functionality is verified by using Synopsys HSPICE 2008.03 Tool.

Area, Dadda algorithm, Delay, Power, Wallace tree multiplier.

"DESIGN OF TRANSISTOR LEVEL 4-BIT X 4-BIT FAST MULTIPLIER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.310-318, April-2019, Available :http://www.jetir.org/papers/JETIRBC06048.pdf

"DESIGN OF TRANSISTOR LEVEL 4-BIT X 4-BIT FAST MULTIPLIER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp310-318, April-2019, Available at : http://www.jetir.org/papers/JETIRBC06048.pdf