• R.Janaki
• K. Sivasankari

The recent VLSI circuits development necessitate device miniaturization as well as intricate manufacturing for their fabrication. This however has led to greater process variation and higher probability of the defects and consequently has worsened yield. To improve the functionality of IC by removing the defects, there are various proposed ideas which reduces difficulty in identifying faults. Many ATPG algorithms were employed in olden days to improve IC functionality. To get better accuracy, we proposed an algorithm called pseudo random bit sequence(PRBS). Unlike existing methods, this technique does not use any diagnostic test generation, circuit modification or mitre-based approach. This is useful in analysing the performance level in terms of area, power and delay.

fault detection, ATPG tools, PRBS, diagnostic test set, faulty location, test set generation.

"FAULT DETECTION IN COMBINATORIAL CIRCUITS USING ATPG", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.252-258, April-2019, Available :http://www.jetir.org/papers/JETIRBF06050.pdf

"FAULT DETECTION IN COMBINATORIAL CIRCUITS USING ATPG", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp252-258, April-2019, Available at : http://www.jetir.org/papers/JETIRBF06050.pdf