• P.D HARSHITHA
• ANURADHA J P

Power Analysis Attack (PAA) are a class of Side Channel Attacks (SCA) which is based on power consumption measurements whose major concern is the protection of secret data stored in cryptographic devices. In this paper, we introduce the concept of Secure Double Rate Registers (SDRR) as a Register Transfer Level (RTL) countermeasure in order to increase the security of cryptographic devices against PAA. SDRR is exploited in AES 128 bit architecture, the random data in the entire clock cycle is evaluated by the combinational path. One of the main advantage is that our technique does not require duplication of combinational path to process the random data thereby limiting area overhead unlike previous RTL countermeasures. This paper compares the implementation results for Rijndael algorithm, conventional AES algorithm with normal registers and AES algorithm with SDRR. It is found that with the use of SDRR the security, delay and power has been improved. Different approach is followed for S-box operation in AES algorithm which helps us to reduce the usage of memory. This proposed system is implemented, simulated using V9erilog HDL and synthesized by Xilinx tool.

Hardware Description Language (HDL), Power Analysis Attack (PAA), Register Transfer Level (RTL), Secure Double Rate Register (SDRR), Side Channel Attacks (SCA)

"AES design based on Secure Double Rate Registers (SDRR)", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.58-61, May-2019, Available :http://www.jetir.org/papers/JETIRCJ06013.pdf

"AES design based on Secure Double Rate Registers (SDRR)", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp58-61, May-2019, Available at : http://www.jetir.org/papers/JETIRCJ06013.pdf