• Prinkle Talan
• Anshul Tyagi

This research paper is about the designing of I2C communication protocol single master using Verilog language. This is a bidirectional, two wired serial bus which is used to transport the data between integrated circuits. Slave devices are interfaced to the microcontroller with the help of the I2C bus. The protocol concept comes into the picture for reducing the hardware complexity and power consumption. The I2C protocol used to connect a maximum of 128 devices that are all connected to communicate with the SCL and SDL lines of the master unit as well as the slave devices. I2C Module and its test bench is simulated in modelsim as well as in Xilinx ISE.

I2CBusProtocol, SDA, SCL, Verilog, ModelSim

"I2C BUS PROTOCOL USING VERILOG ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.85-89, June-2019, Available :http://www.jetir.org/papers/JETIRCO06018.pdf

"I2C BUS PROTOCOL USING VERILOG ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp85-89, June-2019, Available at : http://www.jetir.org/papers/JETIRCO06018.pdf