• Maninder Bir Singh Gulshan
• Priyansha Chichra
• Manasvi Grover
• Shruti Awasthi

In Today’s market, energy consumption to perform any task is of utmost importance. Life of battery operated devices can be enhanced by considering dynamic and leakage power as the primary goal for VLSI circuits. Electronic industries have developed various technologies focussing on size compactness for power reduction. This paper concentrates mainly on static power dissipation. There are eight techniques that are introduced in this paper which lowers the leakage power in the circuit. Paper concentrates on the static power dissipation which is caused by subthreshold voltage and current. Realization of these circuits is done using VLSI designing tool TannerEDA 11.2.

"Optimisation Techniques for Static Power Dissipation in VLSI Circuits", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.98-104, June-2019, Available :http://www.jetir.org/papers/JETIRCO06021.pdf

"Optimisation Techniques for Static Power Dissipation in VLSI Circuits", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp98-104, June-2019, Available at : http://www.jetir.org/papers/JETIRCO06021.pdf