• Steffi Mary Peter
• Dr. Susan R. J.

Due to their flexibility, re-configurability and ca- pacity, SRAM based FPGAs are becoming increasingly suitable for avionics and space applications. But soft errors are a major concern for space electronics. This work focus on a novel protection technique for a 64-bit dual port register file which utilizes the duplicated memories in an efficient manner to convert the inherent register file duplication into a real time fault tolerant memory structure for the soft processors. It uses parity-based error detection and switching (multiplexing) logic. This error masking approach can handle single bit errors and reduce the cost in terms of hardware overhead compared to the error correcting approaches like Hamming codes and Decimal Matrix codes. The delay of this error masking approach is slightly more which can be reduced by replacing the parity based error detection by hamming codes. These are simulated in Xilinx ISE Design Suite 14.1.

Soft processors, Soft errors, Fault injection

"Error Masking Technique For Register File In Xilinx FPGA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.207-212, May 2019, Available :http://www.jetir.org/papers/JETIRCV06041.pdf

"Error Masking Technique For Register File In Xilinx FPGA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp207-212, May 2019, Available at : http://www.jetir.org/papers/JETIRCV06041.pdf