• Neethu Prakash
• Prof. Riyas K S

Now a days, low-power high-speed ADCs are inte-gral parts of a variety of applications such as handheld devices. Comparators are the key building blocks of different types of ADCs. Several years ago, CMOS amplifiers were used as static comparators, although they suffer from very high power consumption (since they are always on) and inherent limited speed. In the proposed comparator, pMOS latch and pMOS preamplifier in addition to a small cross-coupled circuit are used with a special clocking pattern to adjust the preamplifier gain. The clocking pattern provides enough preamplifier gain; since pMOS transistors are used at the input of the latch, and the cross-coupled circuit is employed to keep the common mode voltage of the preamplifier outputs at a low level. It is shown that the proposed comparator reduces the power consumption by half while increasing the speed. Moreover, it operates at large input common-mode voltages close to VDD, although pMOS transistors are used at the input of the comparator. As another benefit, the preamplification delay can be set to its optimum value to have a better comparison speed and reduce excess power consumption. However, in the conventional and other comparators, this delay is fixed to a value which is far from its optimum point. As a result, the proposed comparator is a good candidate for precise low power high-speed applications. Deactivating the preamplifier after the optimum delay reduces the power consumption significantly. Therefore, it reduces the power consumption and improves the speed. The proposed structure can also be implemented using nMOS transistors, i.e., latch and preamplifier with input Nmos transistors. This will result in a higher speed because of the inherent superiority of nMOS transistors over pMOS ones. Using this comparator an SAR ADC is made. The tool used is Cadence.

Dynamic comparator, high speed, low power , two- stage comparator.

"SAR ADC Using Low Power High Speed Comparator for Precise Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.224-229, May 2019, Available :http://www.jetir.org/papers/JETIRCV06044.pdf

"SAR ADC Using Low Power High Speed Comparator for Precise Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp224-229, May 2019, Available at : http://www.jetir.org/papers/JETIRCV06044.pdf