UGC Approved Journal no 63975

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 5 Issue 8
August-2018
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIRD006041


Registration ID:
187034

Page Number

288-290

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Title

Implementation of Advanced Encryption Standard in Vivado Design Suite

Abstract

System On Chip (SoC) are devices which have a FPGA fabric and a processor in its architecture. SoC are used in remote applications where human intervention is not possible. In such circumstances reconfiguration of the devices are required which can be done on the FPGA fabric. One application where this technique can be used is Advanced encryption standard (AES) is a cryptographic technique where the plain text is of 128 bit. The key used for encryption are of different lengths like 128 bit, 192 bit and 256 bit. The keys are chosen according to the kind of encryption needed. This paper describes the implementation of AES in Vivado with the key length of 128 bits. The implementation of the design is placing the design on the FPGA fabric and the wiring connections. The proposed design is realised using XILINX Vivado 2017.1.

Key Words

System on chip, reconfigurable logic, partial reconfiguration, FPGA, key length, Intellectual property

Cite This Article

"Implementation of Advanced Encryption Standard in Vivado Design Suite", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 8, page no.288-290, August-2018, Available :http://www.jetir.org/papers/JETIRD006041.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Implementation of Advanced Encryption Standard in Vivado Design Suite", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 8, page no. pp288-290, August-2018, Available at : http://www.jetir.org/papers/JETIRD006041.pdf

Publication Details

Published Paper ID: JETIRD006041
Registration ID: 187034
Published In: Volume 5 | Issue 8 | Year August-2018
DOI (Digital Object Identifier):
Page No: 288-290
Country: Chennai, Tamilnadu, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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