• Dr.K.Ragini
• B.Neerajakshi

Multiplier is one of the most important arithmetic modules in the fast computing applications. Multipliers and their associated circuits like half adders, full adders and accumulators consume a significant portion of most high speed applications. In order to reduce the hardware which ultimately reduces an area, power and propagation delay, efficient full adders are used in the multipliers. They also reduce the power and propagation delay of the multiplier. In this paper 4x4 multiplier is designed using Dadda algorithm and 10T full adder. Use of Dadda algorithm reduces 10.47% of the power dissipation, 27.67% of the propagation delay and 35.34% power delay product compared to Array multiplier. The simulations are performed using Tanner EDA of 45nm technology.

Multiplier, Full adder, Half Adder, Array, Wallace, Vedic, Dadda, Power dissipation, Propagation Delay, Power delay product.

"Design and Implementation of 4x4 bit Multiplier using Dadda Algorithm", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.122-131, June 2019, Available :http://www.jetir.org/papers/JETIRDC06021.pdf

"Design and Implementation of 4x4 bit Multiplier using Dadda Algorithm", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp122-131, June 2019, Available at : http://www.jetir.org/papers/JETIRDC06021.pdf