• N. VINOD KUMAR
• P. MADHU KUMAR
• AVINASH YADLAPATI

Asynchronous FIFO is a memory file which uses synchronization for reading and writing with different clocks, by performing the conditions of overrun and underrun. In essence, the transfer of data from read domain to write domain with different frequencies. To generate overrun and underrun status flags the synchronization takes place with the help of “preceding operation” of both the write and read pointers. In this design the gray code converters are used to reduce switching activity and the low power DFT technique was applied by considering the two phases that is scan insertion and ATPG Simulations. This design is executed by using synthesizable Verilog RTL Code and verified with xilinx ISE simulator.

Asynchronous FIFO, synchronization, overrun, underrun, status flags, gray code converter, Design for test, RTL Code.

"LOW POWER DFT IMPLEMENTATION FOR ASYNCHRONOUS FIFO", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.203-209, June 2019, Available :http://www.jetir.org/papers/JETIRDC06036.pdf

"LOW POWER DFT IMPLEMENTATION FOR ASYNCHRONOUS FIFO", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp203-209, June 2019, Available at : http://www.jetir.org/papers/JETIRDC06036.pdf