• Sanjeet K Sinha
• -

Abstract:- Power consumption is one of the important aspect of ant digital electronic circuit. In digital circuits all the Boolean expressions are implemented through logic gates, i.e with NOT. AND, OR, NAND and NOR gates. Adder is a basic combinational circuit which is widely used for addition in digital circuits. In this paper A combinational circuit in terms of half adder is implemented and analyzed for the power and it is found that very less power is consumed when we will implement it with the help of CMOS logic.

CMOS Based Arithmetic Circuit for Low Power

"CMOS Based Arithmetic Circuit for Low Power ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 1, page no.1265-1268, January 2019, Available :http://www.jetir.org/papers/JETIRDW06204.pdf

"CMOS Based Arithmetic Circuit for Low Power ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 1, page no. pp1265-1268, January 2019, Available at : http://www.jetir.org/papers/JETIRDW06204.pdf