• Sobhit Saxena
• Sushmita Jha

D-algorithm is one of the most efficient test vector generation technique in the VLSI testing process. In this work a new model of generalized combinational circuit is presented in which users have to choose the gates in the form of binary codes and make their own circuit in a given frame and Verilog code is implemented for generation of test vector for single stuck at fault in the circuit using D-algorithm. The verification of the implemented code is done for four different combinational circuits having the same fault by Xilinx simulator. The obtained results shows that the proposed model is working fine.

Verilog, Combinational Circuits

"Verilog Implementation of D-Algorithm for Testing of Combinational Circuits", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 1, page no.1663-1667, January 2019, Available :http://www.jetir.org/papers/JETIRDW06273.pdf

"Verilog Implementation of D-Algorithm for Testing of Combinational Circuits", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 1, page no. pp1663-1667, January 2019, Available at : http://www.jetir.org/papers/JETIRDW06273.pdf