• Ashish Mulajkar
• Govind Singh Patel

Network on a chip is a concept in which a single silicon chip is used to implement the commu-nication features of large-scale to very large-scale integration systems. For high-end System on Chip designs, Network on Chip is considered the best integrated solution. NoC has several ad-vantages over dedicated wiring and buses i.e. increased bandwidth, low latency, less power consumption and scalability. Reduction in the latency (end-to-end latency and network latency), loss probability, energy consumption and response time are the basic parameters which are con-sidered by the researchers for the optimization of the networks-on-chip topologies. In this paper we review the most popular technologies and also some recent topologies for interconnection networks. We study their performance and summarize their strengths & weakness.

System on Chip, Network on Chip, Optimization, Topologies

"Performance Analysis of various Parameters of Network-on-chip (NoC) for different Topologies", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 1, page no.389-397, January 2019, Available :http://www.jetir.org/papers/JETIRDX06061.pdf

"Performance Analysis of various Parameters of Network-on-chip (NoC) for different Topologies", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 1, page no. pp389-397, January 2019, Available at : http://www.jetir.org/papers/JETIRDX06061.pdf