• Shailesh Mishra
• MANISHA YADAV
• NUPUR KESARWANI

Critical role of any digital system is played by the multiplier. In mathematics, Veda provides one line, fastest processor along with fast cross-checking method. It is most important to implement faster multiplier occupying less area and consuming less power. VEDIC Mathematics is mathematical detail of 'Sixteen Simple Mathematical formula from the Vedas' as release by Sri Bharati Krishna Tirtha. The implementation of the Floating-point multiplier is done by using Vedic multiplication methods. For mantissa multiplication we are using Urdhvatriyakbhyam formula. The cases of underflow and overflow would be solved. The multiplier's input in 32bit IEEE 754 outlay. We implement these multipliers using VHDL. For simulation of our work Xilinx ISE tool i.e. amenable for synthesis tool is used and Modalism 10.2a is also used.

Mathematics of Vedic, a formula of UrdhvaTriyakbhyam, Floating-Point multiplier, precision

"Design and implementation of vedic multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 12, page no.1203-1207, December 2018, Available :http://www.jetir.org/papers/JETIREB06145.pdf

"Design and implementation of vedic multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 12, page no. pp1203-1207, December 2018, Available at : http://www.jetir.org/papers/JETIREB06145.pdf