• Aman Ganesh
• Devineni Gireesh Kumar

A new topology of a symmetric single-phase multilevel inverter with the less number of semiconductor switches and optimized low-frequency control methods to optimize the Total Harmonic Distortion is proposed in this paper. A nine level single phase output is obtained by eight numbers of active semiconductor switches, four diodes and four capacitors from two symmetrical dc sources. The selected harmonic order in the output voltage is eliminated by the PWM (SHE-PWM) based on selective harmonic elimination. To optimize the switching angles, an ant colony optimization is applied. The proposed SHE-PWM and ant optimization are implemented and tested for THD on the SIMULINK platform. The proposed approach offers less THD and is best suited to high-power applications with medium voltage.

THD, SHE-PWM, ACO, Multi- Level Inverter

"Selective Harmonic Elimination based THD Minimization of a symmetric 9- Level Inverter using Ant Colony Optimization", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 3, page no.1542-1546, March-2019, Available :http://www.jetir.org/papers/JETIREL06236.pdf

"Selective Harmonic Elimination based THD Minimization of a symmetric 9- Level Inverter using Ant Colony Optimization", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 3, page no. pp1542-1546, March-2019, Available at : http://www.jetir.org/papers/JETIREL06236.pdf