UGC Approved Journal no 63975

ISSN: 2349-5162 | ESTD Year : 2014
Call for Paper
Volume 9 | Issue 1 | January 2022

JETIREXPLORE- Search Thousands of research papers



WhatsApp Contact
Click Here

Published in:

Volume 6 Issue 2
February-2019
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

7.95 impact factor calculated by Google scholar

Unique Identifier

Published Paper ID:
JETIREY06085


Registration ID:
312835

Page Number

404-410

Share This Article


Jetir RMS

Title

Designing of Double-Gate MOSFET for Low Power RFID

Authors

Abstract

Recently, dual gate MOSFETs (DGMOSFETs) have been demonstrated to be more ideal for ultra-low force circuit structure due to the improved subthreshold incline and the diminished spillage current contrasted with mass CMOS. In any case, DGMOSFETs for subthreshold circuit configuration have not been highly investigated in contrast with those for solid reversal based structure. In this paper, different setups of DGMOSFETs, for example, tied/free doors and symmetric/topsy-turvy entryway oxide thickness are investigated for ultra-low force and high proficient radio recurrence recognizable proof (RFID) structure. Examination of mass CMOS with DGMOSFETs has been directed in ultra-low force subthreshold computerized rationale structure and rectifier configuration, underscoring the extent of the Nano-scale DGMOSFET innovation for future ultra-low force devices. The DGMOSFET-based subthreshold rationale improves vitality effectiveness by over 40% contrasted with the mass CMOS-based rationale at 32 nm. Among the different DGMOSFET arrangements for RFID rectifiers, symmetric tied-door DGMOSFET has the best force change proficiency and the least force utilization.

Key Words

Autonomous Door DGMOSFET, Gadget/Circuit Co-Structure, High Effective Rectifier for RFID, Subthreshold Rationale, Ultra-Low Force, Uneven DGMOSFET.

Cite This Article

"Designing of Double-Gate MOSFET for Low Power RFID", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 2, page no.404-410, February-2019, Available :http://www.jetir.org/papers/JETIREY06085.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Designing of Double-Gate MOSFET for Low Power RFID", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 2, page no. pp404-410, February-2019, Available at : http://www.jetir.org/papers/JETIREY06085.pdf

Publication Details

Published Paper ID: JETIREY06085
Registration ID: 312835
Published In: Volume 6 | Issue 2 | Year February-2019
DOI (Digital Object Identifier):
Page No: 404-410
Country: -, -, India .
Area: Engineering
ISSN Number: 2349-5162


Preview This Article


Downlaod

Click here for Article Preview

Download PDF

Downloads

000147

Print This Page

Current Call For Paper

Jetir RMS