• Nidhi Malhotra

Recently, dual gate MOSFETs (DGMOSFETs) have been demonstrated to be more ideal for ultra-low force circuit structure due to the improved subthreshold incline and the diminished spillage current contrasted with mass CMOS. In any case, DGMOSFETs for subthreshold circuit configuration have not been highly investigated in contrast with those for solid reversal based structure. In this paper, different setups of DGMOSFETs, for example, tied/free doors and symmetric/topsy-turvy entryway oxide thickness are investigated for ultra-low force and high proficient radio recurrence recognizable proof (RFID) structure. Examination of mass CMOS with DGMOSFETs has been directed in ultra-low force subthreshold computerized rationale structure and rectifier configuration, underscoring the extent of the Nano-scale DGMOSFET innovation for future ultra-low force devices. The DGMOSFET-based subthreshold rationale improves vitality effectiveness by over 40% contrasted with the mass CMOS-based rationale at 32 nm. Among the different DGMOSFET arrangements for RFID rectifiers, symmetric tied-door DGMOSFET has the best force change proficiency and the least force utilization.

Autonomous Door DGMOSFET, Gadget/Circuit Co-Structure, High Effective Rectifier for RFID, Subthreshold Rationale, Ultra-Low Force, Uneven DGMOSFET.

"Designing of Double-Gate MOSFET for Low Power RFID", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 2, page no.404-410, February-2019, Available :http://www.jetir.org/papers/JETIREY06085.pdf

"Designing of Double-Gate MOSFET for Low Power RFID", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 2, page no. pp404-410, February-2019, Available at : http://www.jetir.org/papers/JETIREY06085.pdf