• M Arunkumar Yadhav

Adder circuit is basic part of arithmetic circuits and also Application Specific Integrated Circuits (ASIC). Combination of unique logic styles are used to implement adder circuits. Performance analysis of these circuits is measured worst-case delay, power dissipation and Power Delay Product (PDP). Performance of these circuits is dependent on XOR and XNOR circuits. In this unit, XOR and XNOR implemented using PTL, CPL cross coupled and PTL cross coupled logic styles. The performance analysis of XOR and XNOR circuit is done using Mentor Graphics EDA tool at 130nm technology operating at 1.2V supply voltage and frequency of 1GHz. PTL cross coupled style is having lowest power of 3.42nW; The PTL circuit2 and CPL cross coupled has got lowest worst-case delay for XOR as 9.11ps and XNOR as 17.58ps, respectively and PTL circuit2 is lowest PDP of 0.07aJ.

Pass Transistor Logic (PTL), Complementary Pass Transistor Logic (CPL), Complementary Metal Oxide Semiconductor (CMOS), Transmission Gate (TG), XOR-XNOR circuit.

"Performance Analysis of XOR and XNOR Gates Using Different Logic Styles ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 8, page no.60-64, August-2021, Available :http://www.jetir.org/papers/JETIREZ06013.pdf

"Performance Analysis of XOR and XNOR Gates Using Different Logic Styles ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 8, page no. pp60-64, August-2021, Available at : http://www.jetir.org/papers/JETIREZ06013.pdf