• Monika Mehra
• R P Singh

The design and assessment of 8:1 multiplexers utilizing various adiabatic logics was discussed in our research work. High power consumption in digital circuits is the major factor for Very Large Scale Integration (VLSI) design engineers. In this article, we will show the Complementary Metal Oxide Semiconductor (CMOS)-logical new design for a low power adiabatic 8:1 Multiplexer and De-Multiplexer using a 90 nm technology to match this trend. 2N-2N2P uses a transistor structured cross coupling structure for adiabatic operation and double sleep method, with the features of CMOS and the adiabatic logic family 2N2P. Adiabatic logic families usually employ clocks in several phases. Multi-phase clock accelerates the waste of power in your clock network. Due to the clock skew problems and excessive complexity of the clocks, several adiabatic logics are inadequate for high speed operational design. Thus we focus on recovery of energy with efficient energy clock use in this study work. The adiabatic logic circuit has shown to be of great relevance in the development of applications where energy conservation is a critical component for high efficiency, battery-powered handheld and portable electronics.

Adiabatic Logic, CMOS, Energy Recovery, Logic Family, Multiplexer, Transistors.

"Multiplexer and De-Multiplexer Design Employing Various 90 Nm Technology Adiabatic Logic", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 9, page no.245-250, September 2018, Available :http://www.jetir.org/papers/JETIRFH06042.pdf

"Multiplexer and De-Multiplexer Design Employing Various 90 Nm Technology Adiabatic Logic", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 9, page no. pp245-250, September 2018, Available at : http://www.jetir.org/papers/JETIRFH06042.pdf