• Pappu Deepesh

The main objective Arithmetic and logic unit has been the most significant unit in any electronic devices. In the recent advancement, for an arithmetic and logic unit to be significant it needs to have an efficient algorithmic operation such as Multiplications and addition. Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and pseudorandom bit generator (PRBG) algorithms. Carry save adder (CS3A) is the widely used technique to perform the three-operand addition, Ladner-Fischer adder (LFA) and Han-Carlson adder (HCA). Analysis of the adder performance Moreover, In the proposed Three-operand adder that significantly reduces the critical path delay. Hence, a new high-speed adder architecture is proposed using pre-compute bitwise addition followed by KOGGE-STONE adder to perform the three-operand binary addition that consumes substantially low power and drastically reduces the adder delay .

XILINX ISE , VLSI , Verilog , FPGA

" Design of High-Speed VLSI Architecture of Three-Operand Binary Adder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 6, page no.262-269, June-2024, Available :http://www.jetir.org/papers/JETIRGJ06041.pdf

" Design of High-Speed VLSI Architecture of Three-Operand Binary Adder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 6, page no. pp262-269, June-2024, Available at : http://www.jetir.org/papers/JETIRGJ06041.pdf