• S. Alwyn Rajiv
• M.A. Athika Anjum
• G. Priyadarshini
• K. Priyadharshini

Floating point multiplier plays a very important role in all DSP application can perform computations. In IEEE 754 standard describe the floating point number in single precision method and double precision method. The single precision floating number has the 3 parts, sign parts, exponent part and mantissa part. This mantissa part to perform the 24 bit multiplication, it can done by Vedic algorithm. In this Vedic algorithm adders are essential. With the advances in the VLSI technology, researchers have working on reducing the delay, area and power consumption. In this paper, the design 9bit, 18bit and 36bit of various adders like Carry Look Ahead adder (CLA), Carry Save Adder(CSA), Ripple Carry Adder(RCA), and Kogg Stone Adder (KSA). Further, the performance analysis was done in terms of area and delay. All adders are coded by using Verilog HDL and simulated with Xilinx ISE tool

Ripple Carry Adder(RCA), Carry Save Adder(CSA), Carry Look-ahead Adder(CLA), Kogge Stone Adder(KSA).

"Comparative Study on Performance of various Adders used in Vedic Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.464-467, May-2019, Available :http://www.jetir.org/papers/JETIR1905R69.pdf

"Comparative Study on Performance of various Adders used in Vedic Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp464-467, May-2019, Available at : http://www.jetir.org/papers/JETIR1905R69.pdf