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"Design of Folded Cascode Operational Amplifier Using 1.8micron CMOS Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 1, page no.464-466, January-2018, Available :http://www.jetir.org/papers/JETIR1801089.pdf

• K.Rajesh Kumar
• V.Praveena
• J.Kamal Vijetha
• G.Harikrishna
• Bhavani Kinnara

This paper presents the design and simulation of Low Voltage Folded Cascode CMOS Operational Amplifier using gpdk 0.18µM CMOS technology. The proposed op-amp consists of pair of NMOS transistors as an input differential gain stage, the NMOS differential pair is chosen for low power consumption and also to maintain good UGF. The design is simulated using cadence spectre simulator, under ±1V supply voltage. The proposed design shows 68.6dB gain, Phase margin of 500, UGF of 13.1MHz, with power consumption of 30µW.

Folded Cascode Operational Amplifier, Op-Amp, 180nM CMOS Op-Amp.

"Design of Folded Cascode Operational Amplifier Using 1.8micron CMOS Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 1, page no. pp464-466, January-2018, Available at : http://www.jetir.org/papers/JETIR1801089.pdf