• Keefiat Ahmad shah
• Ritika Singh

Propagation delay and power dissipation is the measure con-cern in designing of a VLSI circuit at 90nm or 45nm technol-ogy. For high performance circuit designing with ability of high speed with low power dissipation the existing technology is modify using an extra NMOS circuit in the existing tech-nology for decreasing the power and delay of the circuit. This research is done in term of decreasing the power and delay of the domino logic circuit using EDA tanner tool. The modified domino logic circuit using CMOS technology is design at s-edit and simulation is done at t-edit and w-edit for getting the result in form of delay, average power, EDP and PDP at vari-ous supply voltages from 1v to 0.5v.

Optimization Of Domino Logic In Terms Of Power dissipation And Delay For High Speed Ap- plications using CMOS

"Optimization Of Domino Logic In Terms Of Power dissipation And Delay For High Speed Ap- plications using CMOS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.110-113, May-2019, Available :http://www.jetir.org/papers/JETIR1905B17.pdf

"Optimization Of Domino Logic In Terms Of Power dissipation And Delay For High Speed Ap- plications using CMOS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp110-113, May-2019, Available at : http://www.jetir.org/papers/JETIR1905B17.pdf