• Mr. Aneesh A
• Mr. Austine Cyriac
• Mr. Shafeek Basheer
• Mr. Jishnu K Mohanan
• Dr. James T G

This paper proposes a design of energy efficient level shifter using dual current mirror in 45nm CMOS technology. The proposed level shifter can convert low logic levels, even subthreshold voltage levels to higher acceptable levels. The proposed dual current mirror structure consisting of a modified wilson current mirror based virtual current mirror section and cascoded current mirror based auxiliary current mirror section. The pre-layout and post-layout (DRC and LVS) simulations are done using cadence® EDA tool. From the transient analysis, it is evident that the proposed design achives 0.3V to 1.1V conversion. It exhibits an average propagation delay of 34.6 pS and a total power dissipation of 1.4 pW, for a 300mV, 50MHz input signal. The total area of the proposed design is 49.2 um2. The proposed energy efficient level shifter using dual current mirror exhibits an improvement of power and delay compared to conventional level shifter designs.

Level shifter, Dual current mirror, Cadence, subthreshold to above threshold level conversion.

"Design of Energy Efficient Level Shifter Using Dual Current Mirror in 45nm CMOS Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.38-43, May-2019, Available :http://www.jetir.org/papers/JETIR1905J07.pdf

"Design of Energy Efficient Level Shifter Using Dual Current Mirror in 45nm CMOS Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp38-43, May-2019, Available at : http://www.jetir.org/papers/JETIR1905J07.pdf