UGC Approved Journal no 63975(19)
New UGC Peer-Reviewed Rules

ISSN: 2349-5162 | ESTD Year : 2014
Volume 13 | Issue 3 | March 2026

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Published in:

Volume 10 Issue 2
February-2023
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
508975


Registration ID:
508975

Page Number

e27-e37

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Title

PROGRAMMABLE ARRAY LOGIC(PAL) AND PROGRAMMABLE LOGIC ARRAY(PLA) USING REVERSIBLE LOGIC GATES

Abstract

Reversible logic is currently a new research area. The goal of this white paper is to design and synthesize programmable array logic (PAL) and programmable logic array (PLA) using reversible logic with minimal quantum cost. A PAL is a programmable logic device consisting of an array of programmable AND gates and fixed OR gates. A PLA is a PLD that contains programmable AND arrays and programmable OR arrays. PLDs are combinational circuits primarily used to implement Boolean functions of interest. Reversible Logic has its applications in various fields such as Quantum Computing, Optical Computing, Nanotechnology, Computer Graphics, and low power VLSI etc., Reversible logic has gained importance in recent years, mainly due to its low power consumption and low heat dissipation characteristics. This article proposes PAL and PLA designs with low heat dissipation and low power consumption. The designed circuits are analyzed in terms of quantum cost, garbage outputs and number of gates. The Circuit was designed and simulated using Xilinx software.

Key Words

PAL, PLA, PLDS, Quantum Cost, Reversible Gates, Garbage Outputs, Number of Gates.

Cite This Article

"PROGRAMMABLE ARRAY LOGIC(PAL) AND PROGRAMMABLE LOGIC ARRAY(PLA) USING REVERSIBLE LOGIC GATES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 2, page no.e27-e37, February-2023, Available :http://www.jetir.org/papers/508975.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"PROGRAMMABLE ARRAY LOGIC(PAL) AND PROGRAMMABLE LOGIC ARRAY(PLA) USING REVERSIBLE LOGIC GATES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 2, page no. ppe27-e37, February-2023, Available at : http://www.jetir.org/papers/508975.pdf

Publication Details

Published Paper ID: 508975
Registration ID: 508975
Published In: Volume 10 | Issue 2 | Year February-2023
DOI (Digital Object Identifier):
Page No: e27-e37
Country: East godavari District, Andhra pradesh, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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