• Peddi Anudeep
• V Dharani
• Vijetha Tummala

Power consumption is a major bottleneck of system performance and it is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flip-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them minimizing a number of clocked transistor is an effective way to reduce capacity of the clock load. To approach this, we propose a conditional data mapping technique which reduces the number of local clocked transistors. A 24% reduction of clock driving power is achieved.

SEQUENTIAL ELEMENTS, EFFICIENT CLOCKING, Conditional Operation

"Design of Sequential Elements with Low Power and Efficient Clocking System", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.1, Issue 7, page no.852-856, December-2014, Available :http://www.jetir.org/papers/JETIR1407050.pdf

"Design of Sequential Elements with Low Power and Efficient Clocking System", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.1, Issue 7, page no. pp852-856, December-2014, Available at : http://www.jetir.org/papers/JETIR1407050.pdf