• Vanditha
• Thippeswamy K H

Implementation of memory efficient scalable video encoder architecture is proposed in this aspect that the quality of the video to be good even though it is scaled down. Apart from that also see that the memory utilized by it to be as less as possible. Here a low complexity and memory efficient architecture is being used for scalable video encoder. The proposed very-large-scale integration architecture of the scalable video encoder is implemented on Field Programmable Gate Array (FPGA).The hardware synthesized using Xilinx ISE (Integrated Software Environment). In this architecture a lossless compression, quality driven bit plane sequencer, size scalability and SNR scalability is done.

Lossless compression; discrete wavelet transform; size scalability; SNR scalability; image compression;

"MEMORYEFFICIENT SCALABLE VIDEO ENCODER ARCHITECTURE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.2, Issue 4, page no.1226-1229, April-2015, Available :http://www.jetir.org/papers/JETIR1504071.pdf

"MEMORYEFFICIENT SCALABLE VIDEO ENCODER ARCHITECTURE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.2, Issue 4, page no. pp1226-1229, April-2015, Available at : http://www.jetir.org/papers/JETIR1504071.pdf