• K.HARIBABU
• MD.ABDUL RAWOOF
• J.NAGARAJU

This paper describes circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. A novel gated-clock-driver tree is then applied to further reduce the activity along the clock distribution network. Moreover, the gated-driver-tree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power. The simplest way to implement a delay buffer is to use shift registers. If the buffer length N is and the word-length is b , then a total of Nb DFFs are required, and it can be quite large if a standard cell for DFF is used. In addition, this approach can consume huge amount of power since on the average Nb/2 binary signals make trans

C- element, delay buffer, first-in-first-out, gated clock, ring counter

"Design A Low Power Delay Buffer Using Gated Driver ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.2, Issue 6, page no.1885-1889, June-2015, Available :http://www.jetir.org/papers/JETIR1506036.pdf

"Design A Low Power Delay Buffer Using Gated Driver ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.2, Issue 6, page no. pp1885-1889, June-2015, Available at : http://www.jetir.org/papers/JETIR1506036.pdf