UGC Approved Journal no 63975

ISSN: 2349-5162 | ESTD Year : 2014
Call for Paper
Volume 8 | Issue 5 | May 2021

JETIREXPLORE- Search Thousands of research papers



WhatsApp Contact
Click Here

Published in:

Volume 3 Issue 5
May-2016
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

7.95 impact factor calculated by Google scholar

Unique Identifier

Published Paper ID:
JETIR1605016


Registration ID:
160180

Page Number

76-80

Share This Article


Jetir RMS

Title

A NOVEL 4-BIT ARITHMETIC LOGIC UNIT DESIGN FOR POWER AND AREA OPTIMIZATION

Abstract

In the modern era, power dissipation and area of the circuit under fabrication has become a major and vital constraint in the electronic industry. The objective of this paper is to reduce the power dissipation in the circuit by using gate diffusion input technique. The purpose of this paper is to design and implementation of Arithmetic & logic unit (ALU) using Gate Diffusion Input (GDI) which is area optimized techniques. Design consist of 4-bit arithmetic and logic unit by GDI technique where the logical operation perform by GDI and arithmetic operations are perform via proposed design. Arithmetic operation such as ADDITION, SUBTRACTION, INCREMENT and logical operation like AND, OR, etc., GDI technique reduces average power consumption and number of transistor than CMOS transistor. The simulation tool used is TANNER EDA 15.0 using 250nm technology with 3.2V as a supply voltage.

Key Words

ARITHMETIC & LOGIC UNIT, GATE DIFFUSION INPUT, FULL ADDER

Cite This Article

"A NOVEL 4-BIT ARITHMETIC LOGIC UNIT DESIGN FOR POWER AND AREA OPTIMIZATION ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.3, Issue 5, page no.76-80, May-2016, Available :http://www.jetir.org/papers/JETIR1605016.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"A NOVEL 4-BIT ARITHMETIC LOGIC UNIT DESIGN FOR POWER AND AREA OPTIMIZATION ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.3, Issue 5, page no. pp76-80, May-2016, Available at : http://www.jetir.org/papers/JETIR1605016.pdf

Publication Details

Published Paper ID: JETIR1605016
Registration ID: 160180
Published In: Volume 3 | Issue 5 | Year May-2016
DOI (Digital Object Identifier):
Page No: 76-80
Country: NAGPUR, MAHARASTRA, INDIA .
Area: Engineering
ISSN Number: 2349-5162


Preview This Article


Downlaod

Click here for Article Preview

Download PDF

Downloads

0002467

Print This Page

Current Call For Paper

Jetir RMS