• ASHWINI K S
• SHANKARA C

The National Institute of Standards and Technology (NIST) has initiated a process to develop a Federal information Processing Standard (FIPS) for the Advanced Encryption Standard (AES), specifying an Advanced Encryption Algorithm to replace the Data Encryption standard (DES) the Expired in 1998. NIST has solicited candidate algorithms for inclusion in AES, resulting in fifteen official candidate algorithms of which Rijndael was chosen as the Advanced Encryption Standard. The Advanced Encryption Standard can be programmed in software or built with pure hardware. However, Field Programmable Gate Arrays (FPGAs) offer a quicker, more customizable solution. This research investigates the AES algorithm with regard to FPGA and the Very High-Speed Integrated Circuit Hardware Description language (VHDL). Altera Max+plus II software is used for simulation and optimization of the synthesizable VHDL code. All the transformations of both Encryptions and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption. Altera ACEX1K Family devices are utilized for hardware evaluation.

Encryption, Decryption, FPGA, DES, AES.

"A VHDL IMPLEMENTATION OF THE ADVANCED ENCRYPTION STANDARD-RIJNDAEL ALGORITHM", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 3, page no.78-84, March-2018, Available :http://www.jetir.org/papers/JETIR1803428.pdf

"A VHDL IMPLEMENTATION OF THE ADVANCED ENCRYPTION STANDARD-RIJNDAEL ALGORITHM", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 3, page no. pp78-84, March-2018, Available at : http://www.jetir.org/papers/JETIR1803428.pdf