• Macha Ashok Kumar
• MR. T. Krishna Moorthy

The Proposed Architecture model is 64 Bit Millions of instruction per second (MIPS) Processor which is a new Instruction Set that is a subset of the MIPS architecture. It derives the advantages of MIPS like simplicity i.e. simple to design and speed increases, MIPS takes Multiple instructions at a time i.e., there should be No Problem of Fetching an Waiting condition here so Speed increases. Besides, since it is a smartly optimized subset of MIPS, it is a smaller version consisting of the most commonly required instructions. Verilog HDL is used to describe design and the Process has been realized using XILINX ISE 14.3 and the Total power is estimated by X Power Analyzer.

"Design And Analysis Of 64 Bit MIPS Processor", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 5, page no.1052-1057, May-2018, Available :http://www.jetir.org/papers/JETIR1805188.pdf

"Design And Analysis Of 64 Bit MIPS Processor", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 5, page no. pp1052-1057, May-2018, Available at : http://www.jetir.org/papers/JETIR1805188.pdf