• kiyandoor kartheek
• M. naresh babu

As the advancement cuts back, contracting geometry and plan estimation, on-chip interconnects are introduced to various commotion sources, for instance, crosstalk coupling, supply voltage change and temperature assortment that reason arbitrary and burst mistakes. In this way, botch revision codes facilitated with uproar diminish systems are combined to make the on-chip interconnects overwhelming against goofs. Single blunder adjustment (SEC) codes are for the most part used to secure data set away in memories and registers. In a couple of uses, for instance, sorting out, a few control bits are added to the data to energize their taking care of. For example, standards to stamp the start or the complete of a bundle are for the most part used. Thusly, it is basic to have SEC codes that guarantee both the information (data) and the related control bits. It is charming for these codes to give brisk deciphering of the control bits, as these are used to choose the getting ready of the data and are customarily on the essential arranging way. In this short, a technique to extend SEC codes to help two or three additional control bits is shown. Notwithstanding diminish delay by rectifying two blunders rather than single mistake rectification.

error correction codes, memory, single error correction codes, double error correction

"detection of error correction codes with fast decoding of critical bits", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 5, page no.1067-1074, May-2018, Available :http://www.jetir.org/papers/JETIR1805191.pdf

"detection of error correction codes with fast decoding of critical bits", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 5, page no. pp1067-1074, May-2018, Available at : http://www.jetir.org/papers/JETIR1805191.pdf