• Palagiri Avaneesh
• Dr . P .Nagarajan

Abstract-Synchronous DRAM (SDRAM) has become one of the most important memories of choice due to its significant features like high speed, burst access and pipelining. The high-end applications like Motorola MPC8260 or Intel Strong Arm uses processors which has the interface to the SDRAM by its processor’s built-in peripheral module. However, for other applications, thereis a need for the controller to provide proper commands for SDRAM such as initialization, read/write operations and memory refresh. But in normal 64-bit controllers only one bank of SDRAM can be accessed at a time so there is a need to access multiple banks to increase read/write access speed. Our work will focus on designing and verifying a 128-bit DDR controller to perform read/write on multiple banks at same time. The proposed design is implemented using Xilinx ISE 14.3.

Synchronous Dynamic Random-Access Memory (SDRAM), Double Data Rate (DDR).

"Design and Functional Verification of DDR SDRAM Controller to Access Multiple Banks", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 5, page no.52-58, May-2018, Available :http://www.jetir.org/papers/JETIR1805198.pdf

"Design and Functional Verification of DDR SDRAM Controller to Access Multiple Banks", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 5, page no. pp52-58, May-2018, Available at : http://www.jetir.org/papers/JETIR1805198.pdf